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AgeCommit message (Expand)Author
2024-01-14updated links and todosHEADmasterAndreas Baumann
2021-02-25updated copyrightAndreas Baumann
2021-01-30improved debug mode (d) for togglingAndreas Baumann
2021-01-02added VIAAndreas Baumann
2020-12-30- 7seg is a subdevice of the VIA 6522 now, registering toAndreas Baumann
2020-12-29- testing of correct cyclesAndreas Baumann
2020-12-28introduced cyclesAndreas Baumann
2020-12-25more testingAndreas Baumann
2020-12-21more testsAndreas Baumann
2020-12-20cleanup and more testsAndreas Baumann
2020-12-19some cleanup and refactoring in testsAndreas Baumann
2020-12-12some more testingAndreas Baumann
2020-12-10some more unit testingAndreas Baumann
2020-12-09some more work on test result generationAndreas Baumann
2020-12-06added testing framework (check)Andreas Baumann
2020-12-05- have some emulation modes for single stepping, breaking, changing emulation...Andreas Baumann
2020-12-03some more opcodes for delay 7-seg exampleAndreas Baumann
2020-11-297-segment display is now drawnAndreas Baumann
2020-11-28addressed initializiation of components and valgrindifiedAndreas Baumann
2020-11-27emulator uses a bus now in the cpu, ROM, RAM and VIA (7-seg) are devices conn...Andreas Baumann
2020-11-26more work on emulator, mainly debug and 7seg stuffAndreas Baumann
2020-11-25some work on emulator, also added gengetopt and cmake support for itAndreas Baumann
2020-11-22more work on emulatorAndreas Baumann
2020-11-21started a simple emulatorAndreas Baumann
2020-11-20some more IRQ workAndreas Baumann
2020-11-19added some docu and linksAndreas Baumann
2020-11-18saveing ALL registers when handling interrupts!Andreas Baumann
2020-11-18some 7-bit IRQ work and testingAndreas Baumann
2020-11-17now the RAM works with 7-segment variables on $0 and $1Andreas Baumann
2020-11-17arduino monitor with pseudo-opcodes on SYNCAndreas Baumann
2020-11-17initial checkinAndreas Baumann