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2024-01-14
updated links and todos
HEAD
master
Andreas Baumann
2021-02-25
updated copyright
Andreas Baumann
2021-01-30
improved debug mode (d) for toggling
Andreas Baumann
2021-01-02
added VIA
Andreas Baumann
2020-12-30
- 7seg is a subdevice of the VIA 6522 now, registering to
Andreas Baumann
2020-12-29
- testing of correct cycles
Andreas Baumann
2020-12-28
introduced cycles
Andreas Baumann
2020-12-25
more testing
Andreas Baumann
2020-12-21
more tests
Andreas Baumann
2020-12-20
cleanup and more tests
Andreas Baumann
2020-12-19
some cleanup and refactoring in tests
Andreas Baumann
2020-12-12
some more testing
Andreas Baumann
2020-12-10
some more unit testing
Andreas Baumann
2020-12-09
some more work on test result generation
Andreas Baumann
2020-12-06
added testing framework (check)
Andreas Baumann
2020-12-05
- have some emulation modes for single stepping, breaking, changing emulation...
Andreas Baumann
2020-12-03
some more opcodes for delay 7-seg example
Andreas Baumann
2020-11-29
7-segment display is now drawn
Andreas Baumann
2020-11-28
addressed initializiation of components and valgrindified
Andreas Baumann
2020-11-27
emulator uses a bus now in the cpu, ROM, RAM and VIA (7-seg) are devices conn...
Andreas Baumann
2020-11-26
more work on emulator, mainly debug and 7seg stuff
Andreas Baumann
2020-11-25
some work on emulator, also added gengetopt and cmake support for it
Andreas Baumann
2020-11-22
more work on emulator
Andreas Baumann
2020-11-21
started a simple emulator
Andreas Baumann
2020-11-20
some more IRQ work
Andreas Baumann
2020-11-19
added some docu and links
Andreas Baumann
2020-11-18
saveing ALL registers when handling interrupts!
Andreas Baumann
2020-11-18
some 7-bit IRQ work and testing
Andreas Baumann
2020-11-17
now the RAM works with 7-segment variables on $0 and $1
Andreas Baumann
2020-11-17
arduino monitor with pseudo-opcodes on SYNC
Andreas Baumann
2020-11-17
initial checkin
Andreas Baumann