#include "7seg.h" #include void seg7_init( seg7_t *seg ) { seg->debug = false; } uint8_t seg7_read( seg7_t *seg, uint16_t addr ) { return 0; } void seg7_write( seg7_t *seg, uint16_t addr, uint8_t data ) { switch( addr ) { case DDRA: seg->ddr = data; break; case PORTA: // write bits from SER into shift register on positive SRCLK if( ( seg->ddr | ( SRCLK & SER ) ) && ( data & SRCLK ) ) { seg->shift = ( seg->shift << 1 ) | ( data & SER ); if( seg->debug ) { fprintf( stderr, "7seg shifting data, data is now %02X\n", seg->shift ); } } // copy shift to latch register on positive RCLK if( ( seg->ddr | RCLK ) && ( data & RCLK ) ) { seg->latch = seg->shift; if( seg->debug ) { fprintf( stderr, "7seg copying %02X from shift to latch\n", seg->latch ); } } break; // ignore writes to other addresses } }