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authorAndreas Baumann <mail@andreasbaumann.cc>2020-11-26 19:55:02 +0100
committerAndreas Baumann <mail@andreasbaumann.cc>2020-11-26 19:55:02 +0100
commit3d77f3f5ad41e931117425f58c74f49c9503bf7b (patch)
tree8165c8f10a1b3b3cec27cfb283ee218e7af3a519 /emu/7seg.c
parent394c9fbb6cc243e46b32aa9e7221b0e6cadd4c13 (diff)
download6502-3d77f3f5ad41e931117425f58c74f49c9503bf7b.tar.gz
6502-3d77f3f5ad41e931117425f58c74f49c9503bf7b.tar.bz2
more work on emulator, mainly debug and 7seg stuff
Diffstat (limited to 'emu/7seg.c')
-rw-r--r--emu/7seg.c43
1 files changed, 43 insertions, 0 deletions
diff --git a/emu/7seg.c b/emu/7seg.c
index e69de29..1aaf5f9 100644
--- a/emu/7seg.c
+++ b/emu/7seg.c
@@ -0,0 +1,43 @@
+#include "7seg.h"
+
+#include <stdio.h>
+
+void seg7_init( seg7_t *seg )
+{
+ seg->debug = false;
+}
+
+uint8_t seg7_read( seg7_t *seg, uint16_t addr )
+{
+ return 0;
+}
+
+void seg7_write( seg7_t *seg, uint16_t addr, uint8_t data )
+{
+ switch( addr ) {
+ case DDRA:
+ seg->ddr = data;
+ break;
+
+ case PORTA:
+ // write bits from SER into shift register on positive SRCLK
+ if( ( seg->ddr | ( SRCLK & SER ) ) && ( data & SRCLK ) ) {
+ seg->shift = ( seg->shift << 1 ) | ( data & SER );
+ if( seg->debug ) {
+ fprintf( stderr, "7seg shifting data, data is now %02X\n", seg->shift );
+ }
+ }
+
+ // copy shift to latch register on positive RCLK
+ if( ( seg->ddr | RCLK ) && ( data & RCLK ) ) {
+ seg->latch = seg->shift;
+ if( seg->debug ) {
+ fprintf( stderr, "7seg copying %02X from shift to latch\n", seg->latch );
+ }
+ }
+
+ break;
+
+ // ignore writes to other addresses
+ }
+}