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authorAndreas Baumann <mail@andreasbaumann.cc>2020-12-30 16:55:06 +0100
committerAndreas Baumann <mail@andreasbaumann.cc>2020-12-30 16:55:06 +0100
commitaff63a211e9b1e397adb9dce726d8153beb96dcd (patch)
tree28f5b85fde65cff328fad0ea1d24fe93e5678b2e /emu/7seg.c
parent53569267c59204f56e4c0fddb669536d28706e5c (diff)
download6502-aff63a211e9b1e397adb9dce726d8153beb96dcd.tar.gz
6502-aff63a211e9b1e397adb9dce726d8153beb96dcd.tar.bz2
- 7seg is a subdevice of the VIA 6522 now, registering to
a small sub-bus
Diffstat (limited to 'emu/7seg.c')
-rw-r--r--emu/7seg.c48
1 files changed, 21 insertions, 27 deletions
diff --git a/emu/7seg.c b/emu/7seg.c
index 787b280..d2b2d20 100644
--- a/emu/7seg.c
+++ b/emu/7seg.c
@@ -17,12 +17,11 @@ static device_vtable_t const seg7_vtable = {
seg7_deinit
};
-void seg7_init( seg7_t *seg, uint16_t addr, bool initialize )
+void seg7_init( seg7_t *seg, bool initialize )
{
device_init( &seg->base, "seg7" );
seg->base.vtable = (device_vtable_t *)&seg7_vtable;
- seg->addr = addr;
seg->debug = false;
if( initialize ) {
@@ -33,39 +32,34 @@ void seg7_init( seg7_t *seg, uint16_t addr, bool initialize )
uint8_t seg7_read( void *obj, uint16_t addr )
{
+ // device is a write-only device
return 0;
}
void seg7_write( void *obj, uint16_t addr, uint8_t data )
{
seg7_t *seg = (seg7_t *)obj;
+
+ // address is not relevant, PORTA is connected to our signals
+ // via a databus
- switch( addr - seg->addr ) {
- case DDRA:
- seg->ddr = data;
- break;
-
- case PORTA:
- // write bits from SER into shift register on positive SRCLK
- if( ( seg->ddr | ( SRCLK & SER ) ) && ( data & SRCLK ) ) {
- seg->shift = ( seg->shift << 1 ) | ( data & SER );
- if( seg->debug ) {
- fprintf( stderr, "7seg shifting data, data is now %02X\n", seg->shift );
- }
- }
-
- // copy shift to latch register on positive RCLK
- if( ( seg->ddr | RCLK ) && ( data & RCLK ) ) {
- seg->latch = seg->shift;
- if( seg->debug ) {
- fprintf( stderr, "7seg copying %02X from shift to latch\n", seg->latch );
- }
- }
-
- break;
-
- // ignore writes to other addresses
+ // write bits from SER into shift register on positive SRCLK
+ if( data & SRCLK ) {
+ seg->shift = ( seg->shift << 1 ) | ( data & SER );
+ if( seg->debug ) {
+ fprintf( stderr, "7seg shifting data, data is now %02X\n", seg->shift );
+ }
}
+
+ // copy shift to latch register on positive RCLK
+ if( data & RCLK ) {
+ seg->latch = seg->shift;
+ if( seg->debug ) {
+ fprintf( stderr, "7seg copying %02X from shift to latch\n", seg->latch );
+ }
+ }
+
+ // ignore writes to other addresses
}
#ifdef WITH_GUI