diff options
Diffstat (limited to 'roms/7seg_print_loop_delay.asm')
| -rw-r--r-- | roms/7seg_print_loop_delay.asm | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/roms/7seg_print_loop_delay.asm b/roms/7seg_print_loop_delay.asm new file mode 100644 index 0000000..82ec4db --- /dev/null +++ b/roms/7seg_print_loop_delay.asm @@ -0,0 +1,90 @@ +PORTA = $6001 +DDRA = $6003 + +SER = %00000001 +RCLK = %00000010 +SRCLK = %00000100 + +COUNTER = $0 + + .org #$f800 + +reset: + ldx #$FF ; initialize call stack to $1FF + txs + + ldx #%00000111 ; set output on 7seg control pins of PORTA + stx DDRA + + ldx #$0 ; initialize 8-bit counter + stx COUNTER + +mainloop: ; main loop, load counter and print it + jsr print7seg + ldx #0 ; ca 500'000 cycles, at 1 Mhz 2 ticks per second + ldy #0 + lda #150 + jsr delay + inc COUNTER + lda COUNTER + jmp mainloop + +print7seg: + ldy #$8 ; 8 bits to shift +loop7seg: + rol a + bcc zerobit ; C=0, bang a zero to SER +onebit: + ldx #(SER) ; C=1, bang a one to SER + stx PORTA + ldx #(SER | SRCLK) + stx PORTA + ldx #(SER) + stx PORTA + jmp next +zerobit: + ldx #$0 ; C=0, bang a zero to SER + stx PORTA + ldx #SRCLK + stx PORTA + ldx #$0 + stx PORTA + jmp next +next: + dey + bne loop7seg + rol a ; restore A register +output: + ldx #0 ; bang RCLK to store output in latch + stx PORTA + ldx #RCLK + stx PORTA + ldx #0 + stx PORTA + rts + +; delay 18+13(65536Y+256A+X) cycles +delay: + iny +delay1: + nop + nop +delay2: + cpx #$1 + dex + sbc #$0 + bcs delay1 + dey + bne delay2 + rts + +nmi: + rti + +irq: + rti + + .org #$fffa + .word nmi + .word reset + .word irq |