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<div class="Bspace4">
<em>April 01, 2006</em><br>
<h5>Dependency Management</h5>
<h2>The irony of Make</h2>
</div>
<div class="Bspace15"><em>John Graham-Cumming</em></div>
<!-- teaser -->
<div class="Bspace15"><span class="greenBlurb">John explores the irony of Make.</span></div>
<!-- end teaser -->
<p>
<i>John is vice president of engineering at Electric Cloud, which
focuses on reducing software build times. He can be contacted at
jgc@electric-cloud.com.</i>
</p><p>
</p><hr>
<p>
</p><p>
</p><p>
</p><p>
Make giveth and Make taketh away. It's ironic that the tool Make,
designed to solve the "I've changed some source now what do I need to
recompile?" problem, creates dependency nightmares.</p>
<p>
</p><p>
Any project larger than a "Hello World" example faces dependency
management problems. Dependencies must be generated and kept up to date
as you add to, modify, and delete from the project. And Make itself
provides no tools for dealing with this problem—all Make provides is a
mechanism for expressing the relationships between <a itxtdid="4050710" target="_blank" href="#" style="border-bottom: medium none; font-weight: bold; text-decoration: none; padding-bottom: 0px; color: darkblue; background-color: transparent; cursor: pointer;" classname="iAs" class="iAs"><nobr>files<img style="border: 0pt none ; margin: 0pt; padding: 0pt; height: 10px; width: 10px; position: relative; top: 1px; left: 1px; float: none; display: inline;" src="makedepend_files/3.gif"></nobr></a> with its familiar<i> target : prerequisite1 prerequisite2... </i>syntax.</p>
<p>
</p><p>
The target of the rule (the file that will be built) appears before the
colon (:) and the files that the target depends upon (called either the
"dependencies" or "prerequisites") appears after the colon (:). For
example:</p>
<p>
</p><blockquote>
foo.o : foo.c header.h<br>
<p>
</p></blockquote>
<p>
</p><p>
has target <i>foo.o</i> and prerequisites <i>foo.c</i> and <i>header.h</i>.</p>
<p>
</p><p>
Even Make's dependency syntax is flawed because it incorporates both
"foo.o must be updated if header.h or foo.c are changed" and "foo.o is
the result of compiling foo.c". Thus, anything to the right of the ":"
is a prerequisite, but the first prerequisite where there's a rule body
(that is, commands) is special—it's the prerequisite that's passed to
the compiler (or other command) to actually generate the target. </p>
<p>
</p><p>
Look at this GNU Make example (I use GNU Make throughout this article
because of its wide platform coverage and large set of features): </p>
<p>
</p><blockquote>
foo.o: foo.c header.h system.h<br>
@echo Compiling $@ from $<...<br>
<p>
</p></blockquote>
<p>
</p><p>
which outputs:</p>
<p>
</p><blockquote>
Compiling foo.o from foo.c...<br>
<p>
</p></blockquote>
<p>
</p><p>
Here, <i>foo.o</i> is built if <i>foo.c</i>, <i>header.h</i>, or <i>system.h</i> change, but the rule also states that <i>foo.o</i> is made from <i>foo.c</i> (in GNU Make terms, the target of the rule to the left side of the ":" is written <i>$@</i> and the first prerequisite is <i>$<</i>). If the example were written like this:</p>
<p>
</p><blockquote>
foo.o: foo.c<br>
foo.o: header.h system.h<br>
@echo Compiling $@ from $<...<br>
<p>
</p></blockquote>
<p>
</p><p>
the output would be:</p>
<p>
</p><blockquote>
Compiling foo.o from header.h...<br>
<p>
</p></blockquote>
<p>
</p><p>
which is clearly wrong. If you want to continue exploring Make's idiosyncrasies with <i>$<</i>, play around with this Makefile:</p>
<p>
</p><blockquote>
foo.o: header.h<br>
foo.o: system.h<br>
foo.o: foo.c<br>
foo.o:<br>
@echo Compiling $@ from $<...<br>
<p>
</p></blockquote>
<p>
</p><p>
and try permuting the first three lines to see how Make's interpretation of the Makefile changes.</p>
<p>
</p><p>
The biggest problem of all is generating these rules for a large
project. In the rest of this article, I use this contrived example
Makefile as a starting point:</p>
<p>
</p><blockquote>
.PHONY: all<br>
all: foo.o bar.o baz.o<br>
<br>
foo.o: foo.c foo.h common.h header.h<br>
bar.o: bar.c bar.h common.h header.h ba.h<br>
baz.o: baz.c baz.h common.h header.h ba.h<br>
<p>
</p></blockquote>
<p>
</p><p>
Three object files (foo.o, bar.o, and baz.o) are built from
corresponding C files (foo.c, bar.c, and baz.c). Each .o file has
dependencies on various header files as expressed in the Makefile. The
Makefile uses GNU Make's built-in rules to perform compilation using
the system's compiler.</p>
<p>
</p><p>
There's no mention here of the final executable being built because I
concentrate on dealing with dependencies between sources and objects.
Relationships between objects are usually easier to maintain by hand as
there are fewer of them and the relationships are part of the product
design.</p>
<p>
</p><p>
Because maintaining any real Makefile by hand is impossible, many
projects use the widely available makedepend program (makedepend is
usually installed on UNIX and CYGWIN systems). makedepend reads C and
C++ files looking at the <i>#include </i>statements, follows the <i>#include</i>s, and builds the dependency lines for you. A basic way of incorporating makedepend in a project is a special <i>depend</i> target:</p>
<p>
</p><blockquote>
.PHONY: all<br>
all: foo.o bar.o baz.o<br>
<br>
SRCS = foo.c bar.c baz.c<br>
<br>
DEPENDS = dependencies.mk<br>
.PHONY: depend<br>
depend:<br>
@makedepend -f - $(SRCS) > $(DEPENDS)<br>
-include $(DEPENDS)<br>
<p>
</p></blockquote>
<p>
</p><p>
Doing <i>makedepend </i>with this Makefile causes the depend rule to execute, which runs makedepend on the sources (defined in the <i>SRCS</i> variable) and outputs the dependency lines to dependencies.mk (defined by the <i>DEPENDS</i> variable).</p>
<p>
</p><p>
The Makefile includes the dependencies lines in its final line. dependencies.mk looks like this:</p>
<p>
</p><blockquote>
# DO NOT DELETE<br>
<br>
foo.o: foo.h header.h common.h<br>
bar.o: bar.h header.h common.h ba.h<br>
baz.o: baz.h header.h common.h ba.h<br>
<p>
</p></blockquote>
<p>
</p><p>
Notice that makedepend doesn't try to define the relationship between
an object file (for example, foo.o) and the source file it is made from
(foo.c). In this case, GNU Make's standard rules automatically find the
related .c file. There are two problems with the makedepend<i> </i>style: </p>
<p>
</p><p>
</p><ul>
<li>Running makedepend can be slow, as every source file has to be searched even if there are no changes.</li>
<li>It's a manual step. Before every make, users have to do <i>makedepend</i> to ensure that the dependencies are correct. </li>
</ul>
<p>
</p><p>
</p><p>
The answer to these problems is automation. Here's a version of the
Makefile that still uses makedepend to generate dependencies, but
automates the process, and only runs makedepend for sources that have
changed: </p>
<p>
</p><blockquote>
.PHONY: all<br>
all: foo.o bar.o baz.o<br>
SRCS = foo.c bar.c baz.c<br>
%.d : %.c<br>
@makedepend -f - $< | sed 's,\($*\.o\)[ :]*,\1<br>
$@ : ,g' > $@<br>
-include $(SRCS:.c=.d)<br>
<p>
</p></blockquote>
<p>
</p><p>
It works by associating a .d file with each .c; for example, foo.o has
a foo.d file that only contains the dependency line for foo.o. Here are
foo.d's contents:</p>
<p>
</p><blockquote>
# DO NOT DELETE<br>
foo.o foo.d : foo.h header.h common.h<br>
<p>
</p></blockquote>
<p>
</p><p>
This line specifies when to rebuild foo.o, but also that foo.d should
be rebuilt under the same conditions—if any of the sources associated
with foo.o change, then foo.d gets rebuilt. foo.c isn't mentioned in
this list because it's mentioned as part of the pattern rule for
rebuilding a .d file (<i>%.d : %.c</i>
means that foo.d gets rebuilt if foo.c itself changes). foo.d got added
to the dependency line created by makedepend using the aforementioned <i>sed</i> magic.</p>
<p>
</p><p>
The final line of the Makefile includes all the .d files: The <i>$(SRCS:.c=.d)</i> macro transforms the list of sources in the <i>SRCS</i> variable by changing the extension from .c to .d. The <i>include</i>
also tells GNU Make to check to see if the .d files need rebuilding.
GNU Make looks to see if there are rules to rebuild included Makefiles
(in this case, the .d files), rebuilds them if necessary (following the
dependencies specified in the Makefile), then restarts. This "Makefile
remaking" feature (see section 3.7 "How Makefiles Are Remade" in the
FSF's GNU Make manual;
http://www.gnu.org/software/make/manual/html_mono/make.html#SEC20)
means that simply typing "make" will rebuild any dependency files that
need rebuilding—but only if the sources have changed. Then, GNU Make
will perform the build, taking into account the new dependencies.</p>
<p>
</p><p>
Unfortunately, this Makefile breaks with a fatal error if a header file
is removed. If header.h is no longer needed and all references to it
are removed from the .c files and the file is removed from disk, this
error occurs when Make is run:</p>
<p>
</p><blockquote>
No rule to make target 'header.h', <br>
needed by 'foo.d'.<br>
<p>
</p></blockquote>
<p>
</p><p>
This happens because header.h is still mentioned in foo.d as being a
prerequisite of foo.d; hence, foo.d cannot be rebuilt. This Catch-22
can be fixed by making the generation of foo.d smarter. The new foo.d
includes the dependencies for foo.o and foo.d separately. foo.d's
dependencies are wrapped in a call to GNU Make's <i>$(wildcard)</i>
function (see section 4.4.3 "The Function Wildcard" in the FSF's GNU
Make manual; http://www.gnu.org/software/make/manual/html_mono/make
.html#SEC33). Here's the new foo.d:</p>
<p>
</p><blockquote>
# DO NOT DELETE<br>
foo.d : <br>
$(wildcard foo.h header.h common.h)<br>
foo.o : foo.h header.h common.h<br>
<p>
</p></blockquote>
<p>
</p><p>
And here's the updated Makefile with a new invocation of <i>makedepend</i>, followed by a <i>sed</i> line that creates the modified .d file:</p>
<p>
</p><blockquote>
.PHONY: all<br>
all: foo.o bar.o baz.o<br>
SRCS = foo.c bar.c baz.c<br>
%.d : %.c<br>
@makedepend -f - $< | sed 's,<br>
\($*\.o\)[ :]*\(.*\),<br>
$@ : $$\(wildcard \2\)\n\1 : \2,g' > $@<br>
-include $(SRCS:.c=.d)<br>
<p>
</p></blockquote>
<p>
</p><p>
Now removing a header file doesn't break the Make: When foo.d is parsed, the dependency line for foo.d is passed through <i>$(wildcard)</i>. When there are no globbing symbols such as "*" or "?" in the filename, <i>$(wildcard) </i>acts
as an existence filter, removing those files that don't exist from the
list. So, if header.h had been removed, the first line of foo.d would
be equivalent to: </p>
<p>
</p><blockquote>
foo.d : foo.h common.h<br>
<p>
</p></blockquote>
<p>
</p><p>
and the Make would work correctly. This example Makefile now works when .c files are added (users just update <i>SRCS</i> and the new .d file is created automatically), when .c files are removed (users update <i>SRCS</i>
and the old .d file is ignored), and when headers are added (because
that requires touching an existing .c or .h, the .d file is
regenerated). And when they are removed, the <i>$(wildcard) </i>hides the deletion and the .d file is regenerated.</p>
<p>
</p><p>
An optimization is to remove the need for GNU Make to restart by
merging the rule that makes the .d file into the rule that makes the .o
file. Because the .d file is updated if (and only if) the .o file needs
to be updated (both are updated when any of the sources for the .o
change), it's possible to have the <i>makedepend</i> occur at the same time as the compilation:</p>
<p>
</p><blockquote>
.PHONY: all<br>
all: foo.o bar.o baz.o<br>
SRCS = foo.c bar.c baz.c<br>
%.o : %.c<br>
@makedepend -f - $< | <br>
sed 's,\($*\.o\)[ :]*\(.*\),<br>
$@ : $$\(wildcard \2\)\n\1 : \2,g' > $*.d<br>
@$(COMPILE.c) -o $@ $<<br>
-include $(SRCS:.c=.d)<br>
<p>
</p></blockquote>
<p>
</p><p>
This rule makes use of <i>$*</i>, another GNU Make variable. <i>$*</i> is the part of the pattern <i>%.c</i> that matches the %. If this rule is building foo.o from foo.c, then <i>$*</i> is just <i>foo</i>. <i>$*</i>
is used to create the name of the .d file that makedepend writes to.
This final version does not use GNU Make's "Makefile remaking" system.
There are no rules for making .d files (they are made as a side effect
of making the .o); hence, GNU Make does not have to restart, providing
the best combination of accuracy and speed possible.</p>
<p>
</p><p>
In general, it's a bad idea to have a rule that makes multiple files
because it's impossible for GNU Make to find the rule that makes a file
if it's created as a side effect of something else. In this case, that
behavior is desired: You want to hide the creation of .d files from GNU
Make so that it doesn't try to make them and then have to restart. A
similar idea was proposed by Tom Tromey, without the <i>$(wildcard) </i>trick,
and more information about building dependency files can be found on
the GNU Make maintainer Paul Smith's web site at
http://make.paulandlesley.org/autodep.html. Another good resource for
any GNU Make developer—once you've purchased the FSF's GNU Make
manual—is Robert Mecklenburg's <i>Managing Projects with GNU Make </i>(O'Reilly & Associates, 2004). </p>
<p>
</p><p>
Finally, it's possible to omit makedepend altogether if you are using the GNU GCC compiler. It has a <i>-MD</i> option that does the work of makedepend at the same time as the compilation:</p>
<p>
</p><blockquote>
.PHONY: all<br>
all: foo.o bar.o baz.o<br>
SRCS = foo.c bar.c baz.c<br>
%.o : %.c<br>
@$(COMPILE.c) -MD -o $@ $<<br>
@sed -i 's,\($*\.o\)[ :]*\(.*\),<br>
$@ : $$\(wildcard<br>
\2\)\n\1 : \2,g' $*.d<br>
-include $(SRCS:.c=.d)<br>
<p>
</p></blockquote>
<p>
</p><p>
For example, the compilation step for foo.o will create foo.d from foo.c and then <i>sed</i> is run on the foo.d to add the extra line for foo.d containing the <i>$(wildcard)</i>.</p>
<p>
</p><p>
The use of GCC <i>-MD</i> is an example of creating
dependencies without using makedepend. There are a number of other
possibilities. For example, GCC has <i>-M </i>and <i>-MM</i> options that just output dependency information (<i>-M</i> outputs all dependencies and <i>-MM</i> omits the system headers because they are unlikely to change).</p>
<p>
</p><p>
Another option is the program fastdep
(http://www.irule.be/bvh/c++/fastdep/), which aims to be a fast
replacement for makedepend. Finally, Windows programmers can use
Microsoft CL's <i>/showincludes </i>option to get include information and build dependency information.</p>
<p>
</p><p>
All of these solutions share some common problems. They only work well
for C and C++ code and need to be modified to handle other languages
(although luckily, not all languages have the same dependency forests
as C and C++). In addition, the files included might change as the
result of preprocessor defines; hence, makedepend (or an equivalent
program) needs to be told about any command line <i>-D</i> defines so that it builds the right dependency information.</p>
<p>
</p><p>
Despite the problems outlined here, these Makefile snippets do provide
a reliable way of keeping C and C++ dependencies up to date
automatically and quickly.</p>
<p>
</p><p>
<b>DDJ</b></p>
<p>
</p><p>
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