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                              Assembly Language

                     address space and addressing modes

                                   summary

       This web page examines addressing modes in assembly language.
   Specific examples of addressing modes from various processors are used
   to illustrate the general nature of assembly language.

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     * [8]table of contents for assembly language section
     * [9]address space
     * [10]address modes

     * [11]absolute address
     * [12]immediate data
     * [13]inherent address
     * [14]register direct
     * [15]register indirect

     * [16]address register indirect
     * [17]address register indirect with postincrement
     * [18]address register indirect with predecrement
     * [19]address register indirect with preincrement
     * [20]address register indirect with postdecrement
     * [21]address register indirect with displacement

     [22]base register

     [23]register indirect with index register
     * [24]address register indirect with index register
     * [25]address register indirect with index register and displacement
     * [26]absolute address with index register

     [27]memory indirect
     * [28]memory indirect post indexed
     * [29]memory indirect pre indexed

     [30]program counter relative
     * [31]program counter indirect with displacement
     * [32]program counter indirect with index and displacement
     * [33]program counter memory indirect postindexed
     * [34]program counter memory indirect preindexed

     [35]further reading: books on assembly language

     [36]related software

     [37]further reading: websites

                                address space

       Address space is the maximum amount of memory that a processor can
   address. Some processors use a multi-level addressing scheme, with main
   memory divided into segments or pages and some or all instructions
   mapping into the current segment(s) or page(s).
     * MIX: 4000 words of storage

                               From [38]memory.

         Main storage is also called memory or internal memory (to
     distinguish from external memory, such as hard drives).

         RAM is Random Access Memory, and is the basic kind of internal
     memory. RAM is called “random access” because the
     processor or computer can access any location in memory (as
     contrasted with sequential access devices, which must be accessed in
     order). RAM has been made from reed relays, transistors, integrated
     circuits, magnetic core, or anything that can hold and store binary
     values (one/zero, plus/minus, open/close, positive/negative,
     high/low, etc.). Most modern RAM is made from integrated circuits.
     At one time the most common kind of memory in mainframes was
     magnetic core, so many older programmers will refer to main memory
     as core memory even when the RAM is made from more modern
     technology. Static RAM is called static because it will continue to
     hold and store information even when power is removed. Magnetic core
     and reed relays are examples of static memory. Dynamic RAM is called
     dynamic because it loses all data when power is removed. Transistors
     and integrated circuits are examples of dynamic memory. It is
     possible to have battery back up for devices that are normally
     dynamic to turn them into static memory.

         ROM is Read Only Memory (it is also random access, but only for
     reads). ROM is typically used to store thigns that will never change
     for the life of the computer, such as low level portions of an
     operating system. Some processors (or variations within processor
     families) might have RAM and/or ROM built into the same chip as the
     processor (normally used for processors used in standalone devices,
     such as arcade video games, ATMs, microwave ovens, car ignition
     systems, etc.). EPROM is Erasable Programmable Read Only Memory, a
     special kind of ROM that can be erased and reprogrammed with
     specialized equipment (but not by the processor it is connected to).
     EPROMs allow makers of industrial devices (and other similar
     equipment) to have the benefits of ROM, yet also allow for updating
     or upgrading the software without having to buy new ROM and throw
     out the old (the EPROMs are collected, erased and rewritten
     centrally, then placed back into the machines).

                                address modes

       The basic addressing modes are: register direct, moving date to or
   from a specific register; register indirect, using a register as a
   pointer to memory; program counter-based, using the program counter as
   a reference point in memory; absolute, in which the memory addressis
   contained in the instruction; and immediate, in which the data is
   contained in the instruction. Some instructions will have an inherent
   or implicit address (usually a specific register or the memory contents
   pointed to by a specific register) that is implied by the instruction
   without explicit declaration.

       One approach to processors places an emphasis on flexibility of
   addressing modes. Some engineers and programmers believe that the real
   power of a processor lies in its addressing modes. Most addressing
   modes can be created by combining two or more basic addressing modes,
   although building the combination in software will usually take more
   time than if the combination addressing mode existed in hardware
   (although there is a trade-off that slows down all operations to allow
   for more complexity).

       In a purely othogonal instruction set, every addressing mode would
   be available for every instruction. In practice, this isn’t the
   case.

       Virtual memory, memory pages, and other hardware mapping methods
   may be layered on top of the addressing modes.

                              absolute address

       In absolute address mode, the effective address in memory is part
   of the instruction. Some processors have full and short versions of
   absolute addressing (with short versions only pointing to a limited
   area in memory, normally starting at memory location zero). Unless
   overridden by hardware for virtual memory mapping, programs that use
   this address mode can not be moved in memory.

                               From [39]memory.

         The most basic form of memory access is absolute addressing, in
     which the program explicitely names the address that is going to be
     used. An address is a numeric label for a specific location in
     memory. The numbering system is usually in bytes and always starts
     counting with zero. The first byte of physical memory is at address
     0, the second byte of physical memory is at address 1, the third
     byte of physical memory is at address 2, etc. Some processors use
     word addressing rather than byte addressing. The theoretical maximum
     address is determined by the address size of a processor (a 16 bit
     address space is limited to no more than 65536 memory locations, a
     32 bit address space is limited to approximately 4 GB of memory
     locations). The actual maximum is limited to the amount of RAM (and
     ROM) physically installed in the computer.

         A programmer assigns specific absolute addresses for data
     structures and program routines. These absolute addresses might be
     assigned arbitrarily or might have to match specific locations
     expected by an operating system. In practice, the assembler or
     complier determines the absolute addresses through an orderly
     predictable assignment scheme (with the ability for the programmer
     to override the compiler’s scheme to assign specific operating
     system mandated addresses).

         This simple approach takes advantage of the fact that the
     compiler or assembler can predict the exact absolute addresses of
     every program instruction or routine and every data structure or
     data element. For almost every processor, absolute addresses are the
     fastest form of memory addressing. The use of absolute addresses
     makes programs run faster and greatly simplifies the task of
     compiling or assembling a program.

         Some hardware instructions or operations rely on fixed absolute
     addresses. For example, when a processor is first turned on, where
     does it start? Most processors have a specific address that is used
     as the address of the first instruction run when the processer is
     first powered on. Some processors provide a method for the start
     address to be changed for future start-ups. Sometimes this is done
     by storing the start address internally (with some method for
     software or external hardware to change this value). For example, on
     power up the Motorola 680x0, the processor loads the interrupt stack
     pointer with the longword value located at address 000 hex, loads
     the program counter with the longword value located at address 004
     hex, then starts execution at the frshly loaded program counter
     location. Sometimes this is done by reading the start address from a
     data line (or other external input) at power-up (and in this case,
     there is usually fixed external hardware that always generates the
     same pre-assigned start address).

         Another common example of hardware related absolute addressing
     is the handling of traps, exceptions, and interrupts. A processor
     often has specific memory addresses set aside for specific kinds of
     traps, exceptions, and interrupts. Using a specific example, a
     divide by zero exception on the Motorola 680x0 produces an exception
     vector number 5, with the address of the exception handler being
     fetched by the hardware from memory address 014 hex.

         Some simple microprocessor operating systems relied heavily on
     absolute addressing. An example would be the [40]MS-DOS expectation
     that the start of a program would always be located at absolute
     memory address x100h (hexadecimal 100, or decimal 256). A typical
     compiler or assembler directive for this would be the ORG directive
     (for “origin”).

         The key disadvantage of absolute addressing is that multiple
     programs clash with each other (expecting to use the same absolute
     memory locations for different and competing purposes).

     * MIX: two byte absolute addresses if I field is zero
     * Motorola 680x0, 68300: 16 bit short and 32 bit long versions;
       syntax: xxx.W or xxx.L

                               immediate data

       In immediate data address mode, the actual data is stored in the
   instruction. The sizes allowed for immediate data vary by processor and
   often by instruction (with some instructions having specific implied
   sizes).
     * Motorola 680x0, 68300: byte (8 bit), word (16 bit), and long word
       (32 bit) versions; sign extended; syntax: #xxx

                              inherent address

       Many instructions will have one or more inherent or implicit
   addresses. These are addresses that are implied by the instruction
   rather than explicitly stated. The two most common forms of inherent
   address are either a specific register or a memory location designated
   by the contents of a specific register.

                               register direct

       In register direct address mode, the source and/or destination is a
   register.

       Many processors distinguish between data and address register
   operations (note, in some cases a general purpose register can act as
   eeither an address or data register).

       In data register direct operations, flags are typically set or
   cleared. Data that is smaller than the register may be sign extended or
   zero filled to fill the entire register, or may be placed only in the
   portion of the register necessary for the size of the data, leaving the
   rest of the register unchanged.
     * Motorola 680x0, 68300: 32 bit data registers; data register direct
       operations set or clear flags; byte (8 bit), word (16 bit), and
       long versions (32 bit), only the low order portion of a destination
       register is changed; syntax: Dn

       In register to register (RR) operations, data is transferred from
   one register to another register or an instruction uses a source and
   destination register.
     * IBM 360/370: two byte instructions with a source and a destination
       register; 32 bit data registers; sets or clear flags; full word (32
       bit) transfers; syntax: source, destination (as just a hexadecimal
       number or as a symbolic name)
     * Motorola 680x0, 68300: instructions with a source and a destination
       register; 32 bit data registers; sets or clears flags; byte (8
       bit), word (16 bit), and long versions (32 bit), only the low order
       portion of a destination register is changed; syntax: Dn, Dn

       In address register direct operations, flags are not normally set
   or cleared. The address is usually sign extended to the full address
   size of the processor.
     * Motorola 680x0, 68300: 32 bit address registers; address register
       direct operations do not modify flags; word (16 bit) and long
       versions (32 bit, 24 bits for the original 68000), word-size
       operands are sign-extended to 32 bits; syntax: An

                              register indirect

       In register indirect address mode, the contents of the designated
   register are used as a pointer to memory. Variations of register
   indirect include the use of post- or pre- increment, post- or pre-
   decrement, and displacements.

       In address register indirect operations, the designated register is
   used as a pointer to memory.
     * Motorola 680x0, 68300: syntax: (An)

       In address register indirect with postincrement operations, the
   designated register is used as a pointer to memory, and then the
   register is incremented by the size of the operation. This is useful
   for a loop where the same or similar operations are performed on
   consecutive locations in memory. This address mode can be combined with
   a complimentary predecrement mode for stack and queue operations.
     * Motorola 680x0, 68300: syntax: (An)+

       In address register indirect with predecrement operations, the
   designated register is decremented by the size of the operations, and
   then the designated register is used as a pointer to memory. This is
   useful for a loop where the same or similar operations are performed on
   consecutive locations in memory. This address mode can be combined with
   a complimentary postincrement mode for stack and queue operations.
     * Motorola 680x0, 68300: syntax: -(An)

       In address register indirect with preincrement operations, the
   designated register is incremented by the size of the operations, and
   then the designated register is used as a pointer to memory. This is
   useful for a loop where the same or similar operations are performed on
   consecutive locations in memory. This address mode can be combined with
   a complimentary postdecrement mode for stack and queue operations.

       In address register indirect with postdecrement operations, the
   designated register is used as a pointer to memory, and then the
   register is decremented by the size of the operation. This is useful
   for a loop where the same or similar operations are performed on
   consecutive locations in memory. This address mode can be combined with
   a complimentary preincrement mode for stack and queue operations.

       In address register indirect with displacement operations, the
   contents of the designated register are modified by adding or
   subtracting a dispacement integer, then used as a pointer to memory.
   The displacement integer is stored in the instruction, and if shorter
   than the length of a the processor’s address space (the normal
   case), sign-extended before addition (or subtraction).
     * Motorola 680x0, 68300: 16 bit displacement integers, sign-extended
       to 32 bits; syntax: d(An)

                               base registers

                               From [41]memory.

         Base pointers (sometimes called segment pointers or page
     pointers) are special hardware registers that point to the start (or
     base) of a particular page or segment of memory. Programs can then
     use an absolute address within a page and either explicitly add the
     absolute address to the contents of a base pointer or rely on the
     hardware to add the two together to form the actual effective
     address of the memory access. Which method was used would depend on
     the processor capabilities and the operatign system design. Hiding
     the base pointer from the application program both made the program
     easier to compile and allowed for the operating system to implement
     program isolation, data/code isolation, protected memory, and other
     sophisticated services.

         As an example, the Intel 80x86 processor has a code segment
     pointer, a data segment pointer, a stack segment pointer, and an
     extra segment pointer. When a program is loaded into memory, an
     operating system running on the Intel 80x86 sets the segment
     pointers with the beginning of the pages assigned for each purpose
     for that particular program. If a program is swapped out, when it
     gets swapped back in, the operating system sets the segment pointers
     to the new memory locations for each segment. The program continues
     to run, without being aware that it has been moved in memory.

                    register indirect with index register

       In a register indirect with index register mode, two registers are
   added together to form the effective address of a pointer to memory.
   These are sometimes called the base register and index register. Many
   processors will have limits on which registers can be used for the base
   register and/or which registers can be used for the index register.

       In address/base register indirect with index register operations,
   the contents of the index register are added to the contents of the
   base address register to form an effective address in memory. Some
   processors allow for designating that less than the full size of the
   index register be used in the computation, with the designated low
   order portion of the index register being sign-extended for the
   effective address computation. Some processors require that a
   designated low order portion of the index register be used in the
   computation, with the designated low order portion of the index
   register being sign-extended for the effective address computation.

       In address/base register indirect with index register and
   displacement operations, the contents of the index register are added
   to the contents of the base address register and then an integer
   displacement is added or subtracted to form an effective address in
   memory. Some processors allow for designating that less than the full
   size of the index register be used in the computation, with the
   designated low order portion of the index register being sign-extended
   for the effective address computation. Some processors require that a
   designated low order portion of the index register be used in the
   computation, with the designated low order portion of the index
   register being sign-extended for the effective address computation. The
   integer displacement is stored in the instruction, and if shorter than
   the length of a the processor’s address space (the normal case),
   sign-extended before addition (or subtraction).
     * Motorola 680x0, 68300: 8 bit, 16 bit, or 32 bit displacement
       integer; index register component can be word (16 bit) or long (32
       bit) and can have a scale factor of 0, 1, 2, 4, or 8; syntax:
       d(An,Xn.s)

                    absolute address with index register

       In absolute address with index register operations, the contents of
   an index register are added to an absolute address to form an effective
   address in memory.
     * MIX: two byte absolute addresses with contents of one of five index
       registers

                               memory indirect

       In memory indirect address mode, a location in memory contains a
   value that is used as a pointer (with or without additional effective
   address computations) to another location in memory.

       In memory indirect postindexed operations, the processor calculates
   an intermediate memory address using a base register and a base
   displacement. The processor accesses the designated memory location,
   and adds the contents of the index register and an outer displacement
   to the memory value to yield the effective address. If either
   displacement and/or the index register is shorter than the length of a
   the processor’s address space (the normal case), each is
   sign-extended before addition (or subtraction). Base and outer
   displacements are stored in the instruction.
     * Motorola 680x0, 68300: 8 bit, 16 bit, or 32 bit base and outer
       displacement integers; index register component can be word (16
       bit) or long (32 bit) and can have a scale factor of 0, 1, 2, 4, or
       8; syntax: ([bAn], Xn.s, od)

       In memory indirect preindexed operations, the processor calculates
   an intermediate memory address using a base register, a base
   displacement, and an index register. The processor accesses the
   designated memory location, and adds an outer displacement to the
   memory value to yield the effective address. If either displacement
   and/or the index register is shorter than the length of a the
   processor’s address space (the normal case), each is sign-extended
   before addition (or subtraction). Base and outer displacements are
   stored in the instruction.
     * Motorola 680x0, 68300: 8 bit, 16 bit, or 32 bit base and outer
       displacement integers; index register component can be word (16
       bit) or long (32 bit) and can have a scale factor of 0, 1, 2, 4, or
       8; syntax: ([bAn, Xn.s], od)

                          program counter relative

       In program counter indirect addressing, the program counter is used
   as a reference for the effective address computation. This is most
   commonly used for short branching relative to the current program
   counter, allowing for object code that can be placed anywhere in
   memory.

                               From [42]memory.

         One approach for making programs relocatable is program counter
     relative addressing. Instead of branching using absolute addresses,
     branches (including subroutine calls, jumps, and other kinds of
     branching) were based on a relative distance from the current
     program counter (which points to the address of the currently
     executing instruction). With PC relative addreses, the program can
     be loaded anywhere in memory and still work correctly. The location
     of routines, subroutines, functions, and constant data can be
     determined by the positive or negative distance from the current
     instruction.

         Program counter relative addressing can also be used for
     determining the address of variables, but then data and code get
     mixed in the same page or segment. At a minimum, mixing data and
     code in the same segment is bad programming practice, and in most
     cases it clashes with more sophisticated hardware systems (such as
     protected memory).

       In program counter indirect with displacement operations, the
   effective address is the sum of the address in the program counter and
   the displacement integer stored in the instruction. If the displacement
   integer is shorter than the length of a the processor’s address
   space (the normal case), it is sign-extended before addition (or
   subtraction).
     * Motorola 680x0, 68300: 16 bit displacement integer; syntax: dPC

       In program counter indirect with index and displacement operations,
   the effective address is the sum of the address in the program counter,
   the contents of the index register, and the displacement integer stored
   in the instruction. If the displacement integer or designated portion
   of the index register is shorter than the length of a the
   processor’s address space (the normal case), each is sign-extended
   before addition (or subtraction).
     * Motorola 680x0, 68300: 8 bit, 16 bit, or 32 bit displacement
       integer; index register component can be word (16 bit) or long (32
       bit) and can have a scale factor of 0, 1, 2, 4, or 8; syntax:
       dPC,Xn

       In program counter memory indirect postindexed operations, the
   processor calculates an intermediate indirect memory address by adding
   a base displacement to the contents of the program counter. The value
   accessed at this memory location is added to the scaled contents of the
   index register and the outer displacement to yield the effective
   address. If either the base or outer displacement integer or designated
   portion of the index register is shorter than the length of a the
   processor’s address space (the normal case), each is sign-extended
   before addition (or subtraction).
     * Motorola 680x0, 68300: 8 bit, 16 bit, or 32 bit base and outer
       displacement integers; index register component can be word (16
       bit) or long (32 bit) and can have a scale factor of 0, 1, 2, 4, or
       8; syntax: ([dPC],Xn.s,od)

       In program counter memory indirect preindexed operations, the
   processor calculates an intermediate indirect memory address by adding
   a base displacement and scaled contents of an index register to the
   contents of the program counter. The value accessed at this memory
   location is added to the outer displacement to yield the effective
   address. If either the base or outer displacement integer or designated
   portion of the index register is shorter than the length of a the
   processor’s address space (the normal case), each is sign-extended
   before addition (or subtraction).
     * Motorola 680x0, 68300: 8 bit, 16 bit, or 32 bit base and outer
       displacement integers; index register component can be word (16
       bit) or long (32 bit) and can have a scale factor of 0, 1, 2, 4, or
       8; syntax: ([dPC,Xn.s],od)

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   4. http://www.google.com/
   5. https://www.osdata.com/system/physical/memory.htm
   6. https://www.osdata.com/topic/milo/milo.html>freeemulatorandassemblylanguageproigramminglessons</a>.</p><palign=
   7. https://www.osdata.com/topic/language/asm.htm
   8. https://www.osdata.com/topic/language/asm/asmintro.htm
   9. https://www.osdata.com/topic/language/asm/address.htm#addressspace
  10. https://www.osdata.com/topic/language/asm/address.htm#addressmodes
  11. https://www.osdata.com/topic/language/asm/address.htm#absoluteaddress
  12. https://www.osdata.com/topic/language/asm/address.htm#immediatedata
  13. https://www.osdata.com/topic/language/asm/address.htm#inherent
  14. https://www.osdata.com/topic/language/asm/address.htm#registerdirect
  15. https://www.osdata.com/topic/language/asm/address.htm#registerindirect
  16. https://www.osdata.com/topic/language/asm/address.htm#addressregisterindirect
  17. https://www.osdata.com/topic/language/asm/address.htm#addressregisterindirectwithpostincrement
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  43. https://www.osdata.com/topic/milo/milo.html>freeemulatorandassemblylanguageproigramminglessons</a>.</p><palign=
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  93. http://www.prntrkmt.org/
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