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#include "interrupts.h"
#include "string.h"
#include "stdio.h"
#include "kernel.h"
// TODO: for now the code segment is the first entry in the boot GDT
#define GDT_CODE_SEGMENT_SELECTOR 8
// the Present bit in a IDT entry
#define IDT_PRESENT_BIT 0x80
// DPL rings
#define KERNEL_RING 0
// types of IDT entries
#define IDT_TYPE_INTERRUPT_GATE 0xE
// offset for hardware interrupts
#define IRQ_BASE 0x20
#define IRQ_BASE_MASTER IRQ_BASE
#define IRQ_BASE_SLAVE IRQ_BASE_MASTER + 8
// PIC constants
#define ICW1_ICW4 0x01 // support a 4th initialization word (ICW4)
#define ICW1_INIT 0x10 // bit indicating initialization of chip
void interrupts_init( interrupt_t *interrupt )
{
memset( interrupt, 0, sizeof( interrupt_t ) );
for( int i = 0; i < NOF_INTERRUPT_GATES; i++ ) {
interrupts_register_interrupt( interrupt, i, GDT_CODE_SEGMENT_SELECTOR,
&interrupts_ignore_request, KERNEL_RING, IDT_TYPE_INTERRUPT_GATE );
}
// divide-by-zero exception 0x00
interrupts_register_interrupt( interrupt, 0x00, GDT_CODE_SEGMENT_SELECTOR,
&interrupts_handle_exception_0x00, KERNEL_RING, IDT_TYPE_INTERRUPT_GATE );
// IRQ 0 - PIT - programmable interrupt timer
interrupts_register_interrupt( interrupt, IRQ_BASE + 0x00, GDT_CODE_SEGMENT_SELECTOR,
&interrupts_handle_irq_0x00, KERNEL_RING, IDT_TYPE_INTERRUPT_GATE );
// IRQ 1 - keyboard
interrupts_register_interrupt( interrupt, IRQ_BASE + 0x00, GDT_CODE_SEGMENT_SELECTOR,
&interrupts_handle_irq_0x00, KERNEL_RING, IDT_TYPE_INTERRUPT_GATE );
port8_init( &interrupt->PIC_master_control, 0x20 );
port8_init( &interrupt->PIC_master_data, 0x21 );
port8_init( &interrupt->PIC_slave_control, 0xA0 );
port8_init( &interrupt->PIC_slave_data, 0xA1 );
// initialize hardware management PICs (ICW1)
port8_write( &interrupt->PIC_master_control, ICW1_ICW4 | ICW1_INIT );
port8_write( &interrupt->PIC_slave_control, ICW1_ICW4 | ICW1_INIT );
// set IRQ base of both PICS (ICW2)
port8_write( &interrupt->PIC_master_data, IRQ_BASE_MASTER );
port8_write( &interrupt->PIC_slave_data, IRQ_BASE_SLAVE );
// tell CPU where the IDT is
interrupt->idt_pointer.size = 256 * sizeof( interrupt_gate_descriptor_t ) - 1;
interrupt->idt_pointer.base = (uint32_t)interrupt->descriptor_table;
interrupts_load_idt( &interrupt->idt_pointer );
}
void interrupts_register_interrupt( interrupt_t *interrupts,
uint8_t interrupt_no, uint16_t gdt_code_segment_selector,
void (*handler)( ), uint8_t privilege_level, uint8_t descriptor_type )
{
interrupt_gate_descriptor_t *descr = &interrupts->descriptor_table[interrupt_no];
descr->handler_address_low_bits = ( (uint32_t )handler ) & 0xFFFF;
descr->handler_address_high_bits = ( ( (uint32_t )handler ) >> 16 ) & 0xFFFF;
descr->gdt_code_segment_selector = gdt_code_segment_selector;
descr->access = IDT_PRESENT_BIT | (( privilege_level & 0x3 ) << 5 ) | descriptor_type;
descr->reserved = 0;
}
uint32_t interrupts_handle_interrupt( uint8_t interrupt_no, uint32_t esp )
{
kernel_panic( "Unhandled interrupt 0x%X with ESP 0x%X\n", interrupt_no, esp );
// for now, we are using the same stack for kernel and interrupt
// handlers (n task switching)
return esp;
}
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